1. Field of the Invention
The present invention relates generally to a circuit layout methodology for an integrated circuit (IC), and more particularly pertains to a circuit layout methodology for developing a layout for a very large scale integrated circuit (VLSI) with a set of reduced layout grid ground rules. The circuit layout methodology starts with the design rules for a given technology for fabricating an IC, and establishes a new set of layer-specific layout grid values. A circuit layout obeying these new layout grid requirements leads to a significant reduction in data preparation time, cost, and file size. The present invention can be used for migrating an existing VLSI layout to a set of reduced layout grid ground rules. A layout-migration tool can be used to modify an existing IC layout in order to enforce the new layout grid requirements. A layout-optimization application can be used to rescale data, thus changing the layout grid size, and also adjusting the minimum line widths and minimum line spaces, and a shapes-processing application can be used to adjust via sizes, locations and borders.
2. Discussion of the Prior Art
For any given technology for fabricating an IC on a wafer, (e.g. Intel Pentium™ microprocessor), a layout grid is defined for that technology. The layout grid represents the smallest dimensions that can be used by designers in layout data for each level in that technology. For a 130 nanometer (nm) generation technology, that value is approximately 0.01 microns. For wires and vias, this means that their widths and spacing are changed in 0.01 micron increments (e.g. 0.99, 1.00, 1.01 microns).
In addition, each technology for fabricating an IC specifies ground-rule values for minimum line width and minimum line spacing for each metal layer (M1 (the first and lowest metal layer), M2 (the second, next higher metal layer) and for each via layer (V1 (the via layer connecting M1 to M2), V2 (the via layer connecting M2 to M3)), etc. For a 130 nanometer (nm) generation technology, these ground-rule values are:
M1 minimum line width and line space=0.16 microns,
M2 minimum line width and line space=0.20 microns,
M3 minimum line width and line space=0.20 microns,
V1 minimum line width and line space=0.20 microns,
V2 minimum line width and line space=0.20 microns, etc.
For a 65 nm generation CMOS technology, the above values for a 130 nm generation CMOS technology are reduced by approximately one half.
It is apparent that the permitted feature sizes for wiring shapes are much smaller than the sizes actually required to draw wires in a VLSI layout, since for the exemplary 130 nm generation CMOS technology, the grid size is 0.01 microns and the M2 minimum line width and line space is 0.20 microns. The resolution enabled by the manufacturing layout grid size is in some sense unneeded for wiring levels, since the minimum line space and minimum line width ground rules for wires are large multiples of this fine grid size. The grid size is much smaller than the minimum feature size to allow for the use of optical proximity correction (OPC).
The end result of using OPC is that data volume and processing runtime increase unduly during data prep. This ultra-fine grid is necessary for the mask layers that require extensive OPC (such as the layers involved in forming devices) to account for photolithographic and etch problems, but such extensive OPC processing and ultra-fine grids are not normally necessary for the wiring layers.